throwaway000002

If AAPL thinks QCOM doesn't add proportional value to their phone, let them sell their phone without QCOM ip.

Because we all know AAPL takes its proportional percentage of flesh from an app developer for having the audacity to add value to iOS, whilst simultaneously holding back the web.

Hypocrisy all around.

The specific part of your comment, which is true, is, yes, I am essentially warning that you can do your absolute best to raise a child and put their interests (as you see it) ahead of your own, and they still may end up hating you for it.

I'm not, however, going to comment on any other part of your response. I just don't want to get into it.

As a counterpoint to some platitudes expressed here, let me say this: I unequivocally hate my dad. The reasons are complicated, and personal. But there is something I know with absolute certainty. Everything he ever did in relation to me was with the best of intentions, and he always placed my well-being (as seen by him) before his.

Sure, I mostly feel like an ungrateful wretch. And yes, now that he's an old man, I do treat him very poorly and wish he were dead, mainly because it'd save my feelings of guilt with how I treat him.

I wonder if he resents having me. I will never ask him. I fear his reponse, that he'll deny it.

If you're willing to have a kid, I'm one of the ugly corner cases.

I don't have any kids. I'm beyond the age where they're on my radar. Perhaps a relationship with someone a fair bit younger would change that, but I doubt it.

Good luck.

Sure, this is one technique. You could also, akin to jump instructions, have a concept of data locality, versus instruction locality. You can do this is a lot of ways without resorting to something like segmentation, which everybody hates. Trivial would be something like a current "data pointer", which would see useful implicit updates, and well as explicit ones (akin to a long jump).

You sound like an architecture person (I'm not, btw), so maybe you can give the lowdown on this.

Why registers? I haven't studied the Tomasulo algorithm in any detail, but if you're going to do "register renaming", why have registers at all? You could, for example, treat memory as a if-needed-only backing store, and then add a "commit" instruction that commits memory (takes an address, or a range). Sure you need to make changes with how you do mm i/o and protection, but at a basic level: why registers?

I'm glad FPGA's are becoming a thing, and I think we're about a decade or two away from ASICs as a service, because if you're not beholden to tradition, you really can work some magic. Of course I'll be pretty rusty by then, but who knows, maybe medicine will keep me feisty.

I can understand the historical requirements for alignment, the necessary transistors, what not. But, much like branch-delay slots, there is no modern reason to expose this to the programmer. Of course, I gave an exception to atomics, but if you will, they're like memory-mapped communication, and now that all I/O is memory-mapped, with no concept of ports, the (ordering) semantics of memory access becomes really important.

I'm also the weirdo that feels process isolation, memory management, and I/O mechanisms need a rethink. But that's something that would take me forever to get into.

One thing I will say, though, is alignment issues "infect" everything. Assume your architecture doesn't allow misaligned access. Now, all your data has to be naturally aligned. Your structs now have to be aligned to the alignment of the largest sub-structure within them. This is all because code is alignment sensitive. Given a pointer to a struct, generic code is unnecessarily larger. Any why would we care? Communication, of course. If we're exchanging data between systems then idiosyncrasies such as this suddenly become globally visible.

Endian-ness must be little. Byte-aligment a non-issue, and network-bit order should be from bit zero up, with any upper layer need, say for cut-through forwarding, expressed as a data ordering requirement, so for example an IP4 address is not a blind 32-bit word, but specifies the structure of those 32-bits.

I understand. What I mean is that if your word-size is not your addressing-size, you'd better not have a concept of mis-aligned accesses. It's trouble you brought on all by yourself.

I'm probably the only weirdo that thinks this, but if you support byte-addressing you'd better as well be happy with byte-alignment. Atomics being the only place where it's reasonable to be different.

Which brings me to padding. I wonder what percentage of memory of the average 64-bit user's system is padding? I'm afraid of the answer. The heroes of yesteryear could've coded miracles in the ignored spaces in our data.

Thanks Jack for taking the time to respond.

Keeping the faith alive...

I used to be a big champion of RISC-V, just look at my submission history, but I've become increasingly weary due to SiFive's dubious leadership.

1) It's still impossible for anyone to get their hands on an FE310 chip over half-a-year on from the release of the HiFive board.

2) They promised open-source cores, but somehow backtracked due to "customer requests". How does this make any sense? And if so, just have an open-source version, and a closed-source one that, I dunno, has a SiFive logo on the mask.

I was really inspired by them, now I'm mostly dejected. Still, I'm hoping someone like ST takes their peripherals and makes an MCU with a RISC-V.