ruik

There seems to be some bits in Intel PCH chipset datasheets for that: Power Button Override Period (PBOP): This field determines, while the power button remains asserted, how long the PMC will wait before initiating a global reset. Encoding:

000b - 4 seconds

001b - 6 seconds

010b - 8 seconds

011b - 10 seconds

100b - 12 seconds

101b - 14 seconds

Others - Reserved

This bit is reset by DSW_PWROK de-assertion. (edited formatting)

The ACPI specification says: Additionally ACPI defines a fail-safe Off protocol called the “power button override,” which allows the user to initiate an Off sequence in the case where the system software is no longer able to recover the system (the system has hung). ACPI defines that this sequence be initiated by the user pressing the power button for over 4 seconds, at which point the hardware unconditionally sequences the system to the Off state. This logic is represented by the PWRBTN_OR signalcoming into the sleep logic.