There seems to be some bits in Intel PCH chipset datasheets for that: Power Button Override Period (PBOP): This field determines, while the power button remains asserted, how long the PMC will wait before initiating a global reset.
Encoding:
000b - 4 seconds
001b - 6 seconds
010b - 8 seconds
011b - 10 seconds
100b - 12 seconds
101b - 14 seconds
Others - Reserved
This bit is reset by DSW_PWROK de-assertion. (edited formatting)
000b - 4 seconds
001b - 6 seconds
010b - 8 seconds
011b - 10 seconds
100b - 12 seconds
101b - 14 seconds
Others - Reserved
This bit is reset by DSW_PWROK de-assertion. (edited formatting)