redraga

I completely agree with this observation. In fact, you can use this to your advantage to save time. During the pandemic years of 2020 and 2021, Blizzard released "Classic" World of Warcraft and I had this huge itch to play the game. I satisfied it by watching YouTube videos on Classic WoW instead.

Did I waste time watching WoW YouTube videos? Yes. Did I save much more time by tricking my brain into thinking I was playing the game when I actually wasn't? Yes!

Would a public/private signature for videos work in solving such fakes? If not, why not?

I've started playing around with the idea of building a better retirement/goals investment calculator/tracker for Indians.

The retirement calculators available online are almost farcical in their simplicity and assumptions. And the ones offered by professional, fee-only financial advisors (I engaged one) are just clunky, uneasy to use excel sheets. They do the job of course, but I think there has to be an easier, more intuitive way to tracking goals/investments.

I know way too many of my friends and acquaintances - educated, fairly wealthy people - who seem to have almost no idea on how to plan/track goals/retirement. It'd be fantastic if I could make something which helps them and others like them.

I wasn't aware of this. The model actually works great since I've personally accessed multiple papers from INRIA/IRISA from the HAL archives.

I can't really comment on the tradeoffs between specific ISAs since I've mainly worked on micro-arch research (which is ISA agnostic for most of the pipeline).

As for the questions on research into looking at decode complexity v instruction density tradeoff - I'm not aware of any recent work but you've got me excited to go dig up some papers now. I suspect any work done would be fairly old - back in the days when ISA research was active. Similar to compiler front-end work (think lex, yacc, grammar etc..) ISA research is not an active area currently. But maybe it's time to revisit it?

Also, I'm not sure if Huffman encoding is applicable to a fixed-size ISA. Wouldn't it be applicable only in a variable size ISA where you devote smaller size encoding to more frequent instructions?

I can't comment on the economics of it but I can comment on the technical difficulties. The issue for x86 cores is keeping the ROB fed with instructions - no point in building a huge OoO if you can't keep it fed with instructions.

Keeping the ROB full falls on the engineering of the front-end, and here is where CISC v RISC plays a role. The variable length of x86 has implications beyond decode. The BTB design becomes simpler with a RISC ISA since a branch can only lie in certain chunks in a fetched instruction cache line in a RISC design (not so in CISC). RISC also makes other aspects of BPU design simpler - but I digress. Bottom line, Intel and AMD might not have a large ROB due to inherent differences in the front-end which prevent larger size ROBs from being fed with instructions.

(Note that CISC definitely does have it's advantages - especially in large code foot-print server workloads where the dense packing of instructions help - but it might be hindered in typical desktop workloads)

Source: I've worked in front-end CPU micro-architecture research for ~5 years

Yes. TAGE still does better than perceptron, but combining the two is likely to give you the best performance currently. Of course, all this is dependent on area allocated to the predictor and the workloads being run.