claudio_mos

> The first question has to be: why?

There are many reasons. The main one is that no architecture exists that models such a complex ternary processor. At most, there are "on paper" implementations of much less complex architectures; no one has addressed the problem at this level. Having a complete architecture and its hardware implementation now allows us to start developing software on something other than an emulator.

> ---- I don't see any rationale or explanation of the thinking. Is it purely an exercise? Exploration? Is there some algorithm space in which it has an advantage over binary? > -----

No, it's a processor that's available now, both the current hardware implementation (on FPGA) and the Verilog/VHDL description for implementation on other architectures (ASIC?), as well as the specifications made available under license.

>---- Is there a compiler? >----

Hmm, but I mentioned it in the paper; currently, a working cross-assembler (obviously) and a high-level language based on Rust are being designed/built.

>---- How does it compare on Dhrystone or Coremark per LUT compared to a RISC-V core of similar size on the same FPGA? >----

This is an interesting question; the answer is: currently, no. We intend to provide (soon) comparative tests of this type.

I have updated the site with a references section. Here you will find some links to recent studies on native ternary semiconductors.

Oh, I don't think at all that this method of operation (Tomasulo?) is remotely close to a real dataflow in terms of efficiency and complexity. But as I wrote, dataflow is another story ;)

ok, now i can say for sure, you didn't read the site well at all. you didn't even read my answers well. maybe you would have understood that now mosfet level design is already happening but it only concerns the CPU (if you want to deal with the mainboard, fine, you will have read that it is open hardware). I don't understand what you need such low level technical details for, it is obvious that i am not here to share them. If you want to make a CPU do it too, in the end we will see who did it better. now excuse me I have some serious work to do.

Thanks! Ternary data is definitely more efficient than binary, regardless of your use, not just for AI. I honestly don't know if it's faster, can you give me information on where you read that?

I imagine it's possible even if quite difficult to merge the two architectures, but maybe it's really easier to start everything from scratch as far as hardware is concerned.

What do you mean by ternary addressing? The address bus is also in ternary so even in this case fewer wires and more addresses available!

Just as simple: it's easy to have positive voltage, negative voltage or no voltage ;)

Thanks for the help, maybe we need someone to write the basic software right now!

Ok, maybe that's not clear, probably my not-so-perfect English is a problem. The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and ternary arithmetic. This may eventually form the basis for the dataflow processor, but right now I'm talking about and building the ternary processor (Of course dataflow architectures are quite different and unconventional, but that's in the future, I'm not talking about it now).

As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA. It already comes to the FPGA in "ternary encoded bunary" from external circuits.

Yes, the serial buffer is included in the motherboard. The problem is not so much for OUT but for IN, if the buffer fills up.

As for the bus addresses, the counter program starts from the lowest address. The mainboard obviously knows how much RAM is present and performs a translation to the first available low address. Nothing transcendental.

I did not understand the connection with VonNeumann architectures, this is a classic vonneumann architecture, only that the information is in base 3...

Anyway you seem to be really very expert, certainly more than me (I am mainly a programmer and I had to learn these things at low level practically by myself), you could actively help the project...

Yes, of course to load a character I use LD.T

Uhmm..actually the OUT instruction ends immediately after its normal cycle. the character is sent to the mainboard that reads it and puts it in a buffer and passes from a buffer. (it's more complex, if you want we can discuss)

The external BUS is 24 trit. the motherboard converts it by encoding it into binary and the data is stored on 48bit RAM. We don't have native ternary RAM yet unfortunately, but it was the only way to have some memory and use the processor.

I don't quite understand what idea I describe in the OP you're referring to. And I don't understand what ternary operations might be useful for neural networks (we've had contact with Korean researchers asking about this processor for neural networks).

The specifications obviously exist, but I don't think it's a good idea to put them here on a generic site! I think the marketing phase will take a while longer and as you may have read on the site, we're still fixing things here and there and we need a marketing apparatus.