Ok, maybe that's not clear, probably my not-so-perfect English is a problem.
The dataflow architecture was the initial idea. What I'm talking about now is the ternary processor, a normal VonNeumann processor with ternary data and ternary arithmetic.
This may eventually form the basis for the dataflow processor, but right now I'm talking about and building the ternary processor (Of course dataflow architectures are quite different and unconventional, but that's in the future, I'm not talking about it now).
As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA.
It already comes to the FPGA in "ternary encoded bunary" from external circuits.
As for address management, as I said the mainboard does it all, but I didn't care to go that low in detail, it's all a simple VHDL function in an FPGA. It already comes to the FPGA in "ternary encoded bunary" from external circuits.