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yatrios
Joined 2 years ago
Karma
72
Submissions
3
Member since
Oct 4
View on Hacker News
Recent submissions
Formal Verification for Verilog Using Yosys
c
cheickdo.github.io
1
yatrios
1 year ago
0
comments
Shift Left Is the Tip of the Iceberg
s
semiengineering.com
181
yatrios
2 years ago
97
comments
Comment · 2 years ago
I find this new path pretty fascinating. Have there been any recent advancements in terms of the signal integrity issue when partitioning these designs? To me these chiplets currently seem to still be very proof of concept and I'm not sure of how feasible this is in large scale designs. Could someone care to clarify?