tfmkevin

There are no separate tools for military use. And, the mil/aero versions of the chips are usually a generation or two behind because of the extra work to make them high-reliability, produce the required documentation, etc.

HLS is real. I've talked with dozens of teams who have successfully used HLS tools such as Mentor's Catapult, Xilinx's Vivado HLS, and Cadence's Stratus for a wide range of ASIC and FPGA projects. They claim they saw compelling benefits in project schedules, architectural flexibility, and overall performance. However, HLS is still (IMHO) a "power tool" for competent digital designers, not a tool that enables a software designer to create hardware. There is too much hardware-specific expertise required to create good HLS-able code and to do the tradeoffs like pipelining, unrolling, memory architecture, etc etc etc.

The "average person" cannot program for it. I've managed teams as large as 60 extremely competent full-time EDA engineers working for years on only the synthesis portion of the problem. It is FAR more complex than, say, developing a compiler. Both Xilinx and Intel have more engineers developing FPGA software tools than they do developing FPGA hardware. It's a common misconception that just any group of competent software engineers could whip out better FPGA tools if they only had access...