mad_ned

I'm still alive. But I've retired or at least taken an extended hiatus from my writing hobby, which in retrospect was probably a pandemic coping mechanism more than a lot of things lol.

I only came here because my in box is blowing up due to the traffic hacker news is driving to my site, and so then I see that this article is like #3 today. Not bad considering I don't really remember writing it!

More Marshmallows!

It's a rainy Saturday here, thought I'd give this one a second shot since the mood seemed right!

This is a great resource for aspiring FPGA tinkerers like me. Thanks for sharing!

Wish granted! @the.bessie.report on Instagram

haha yes, excellent suggestions! I did think about ternary logic actually but I don't know of an FPGA that supports it. I considered creating like a primitive that burns 2 register bits to approximate it even, and just throw away the 4th state and pretend I have 3-state logic on all the layers above. but i have enough on my hands just trying to get the stupid timing working on a simple CPU. Im not actually a CPU designer so I dont really know what I'm doing lol.