jmpe

> The 100 is a normalized number, it's not the actual number of blocks.

I'm not too sure about that. The only ref I can give is that they use the suffix "Cnt_Tot" which means "total count". When it's a percentage they denote it as such as in "Perc_Rated_Life_Used" and "Workld_Host_Reads_Perc". Don't be surprised by the low count (100).

You wouldn't happen to know how close these ARM cores are to LPC1xxx or STM32? Would it be worthwhile to port Chibios to them?

First: I jumped into the comments before reading the article.

I have quite some experience with Flash in the form of eMMC and SD/CF. SSDs aren't that much different from those on the low level.

The controller that comes with the flash storage contains a core that manages the bad blocks. Comparable to bad sector management on HD. The software these controllers run contain a lot of rules of thumb to manage bad blocks, which is where these full failures come from IMO.

Each controller has access to a pool of reserve blocks that are used when bad blocks are detected. Once those run out the embedded software starts showing weird behavior when using the device and shortly after there's a complete fail.

I think the pool of reserve blocks is "Used_Rsvd_Blk_Cnt_Tot" in your list. Apparently there are 100, of which you consumed 0. There's a threshold at 10 so I assume that's where the diagnostics software will warn you.

The 4 & 5LP are 32 bit ARM, the 1 & 3 are 8 bit.

A TI-73 or TI-83 is $20 or less on eBay.

HP's claim isn't rediculous if you consider that they're not developing memristor tech to replace flash storage. They want to unify mass storage drives with DRAM. You do need an O.S. that can be partially rewritten, because the system can remain in the state where you switched it off. Richard Stanley Williams is the name to Google if you want insight into their roadmap.

Correct, it was wrong of me to point to "architectures" that lack Neon; you're correct in your reply. I should have mentioned specific implementations. My experience with Allwinners without Neon indeed comes from smart TVs and STB. You know your stuff ;)

Anyone experimented with this yet? I'd like to know how this is resolved when the architecture doesn't support Intel's SIMD approach, they map the objects pretty close to the instructions (SIMD.float32x4.sub and the likes).

I'm trying to figure out what happens when you port this to ARM NEON, and how you catch it with architectures that don't support NEON (they often lack them in Marvell and Allwinner).