henrikf

That's very impressive and I'm even more impressed if you can manage to sell tiles at that low price.

PA looks suspiciously similar to SE5004L. I just needed some for my own projects but every distributor is out of stock. I wonder if this is where all of them went?

It was from JLCCNC.

There's not much software. PC calculates PLL register values for correct LO and source output frequencies, and transfers them to the FPGA which writes them to the hardware. FPGA accumulates the downconverted samples from the receiver ADCs. Samples are transferred to PC which calculates ratios of the receiver outputs to get uncorrected S-parameters. scikit-rf Python library is used for calibration and plotting.

I have also had issues with motivation. I had a long pause from about 2019 to 2024 where I didn't work on personal electronics projects because I didn't have enough motivation. This and last year however I have been very productive and it's hard to say what exactly changed, just felt like working on them.

It's not on Github, but I do have schematic at the end of the blog post. vna2 is the previous version.

Thanks for the submission. Author here if you have any questions.

No, it needs to be done manually. It wasn't as tedious as it sounds though. Most of the pins are very close in delay already and there were just few traces that I had to adjust a little.

The FPGA manufacturer has characterized all their package pin delays. It's possible to export a csv file with internal delays of the package for each pin from the FPGA design tool. With Xilinx Vivado it's just File -> Export I/O Ports.

I actually didn't use any expensive test equipment, only oscilloscope and multimeter. Even design and simulation software was all open source.

Expensive signal analyzer or spectrum analyzer would have been useful, but they aren't absolutely necessary. It's possible to use the radar itself for many tests and debugging.

I have tried to limit the projects I do on my own to only the equipment that I have home and open source software.

I built it to see if I could. I didn't have any particular use case in mind.

Putting ground planes on top and bottom layers isn't usually done with high speed PCBs because components are there. There would need to be a cutout on the ground plane near every chip. High speed signals really need continuous ground plane and ICs, especially RF ICs, need short access to ground. Second layer is the best layer to minimize the distance from ICs to ground plane.

That's a mistake in the text. You're correct that layers 2 and 5 are ground planes.

What's open sourced here is the design kit. Designed chips need to be sent to IHP to be manufactured.

SiGe isn't also that useful for military radar applications. Compared to SiGe GaN has much greater breakdown voltage which leads to greater output power and better efficiency. It's possible to get 10 to 100 times more output power from GaN chip compared to SiGe. It isn't really possible to make high performance long range radar with just SiGe although it could be used in some parts of it.