helpbygrace
Joined 15 years ago
Joined 15 years ago
In my experience, even though speedmeter in the instrument panel shows 10mph over, actual GPS speed is around speed limit.
Atom's soft wrap doesn't works well. It seems to count character length in order to split the line.
In my experience, it is quite easy to describing the hardware logic if the architecture is designed well. So, what I mean in "VISIO and Excel are much more important" that the architecture should be concise and cycle accurate. Then verilog coding is just a piece of cake.
Designing hardware is much more important than describing hardware logic itself. IMO, VISIO and Excel are the tools to design hardware logic not Verilog nor like this CLaSH.
But, If this kind of HDL can be used along with Verilog, it might be helpful to build verification IPs.