Recent submissions

Comment · 4 years ago
Can Wachy be used to trace kernel code as well? And would you need to do anything specific to get that to work? (How would Wachy find the kernel sources?)

I was thinking this would be pretty cool to use for debugging device drivers on embedded devices especially w.r.t latency.

Comment · 7 years ago
Since you seem to know, what company would one go to for fabricating a 500nm chip these days at that price?
Comment · 7 years ago
Does the PhantomData type in Rust do what you want? Or are you talking about something slightly different?

https://doc.rust-lang.org/nomicon/phantom-data.html

https://doc.rust-lang.org/std/marker/struct.PhantomData.html

So

  struct Sender<S> {
    /// Actual implementation of network I/O.
    inner: SenderImpl;  
    /// 0-sized field, doesn't exist at runtime.
    state: S;
  }
I believe could become

  struct Sender<S> {
    /// Actual implementation of network I/O.
    inner: SenderImpl;  
    /// 0-sized field, doesn't exist at runtime.
    _marker: PhantomData<S>;
  }
I've never used this PhantomData personally, so this might be wrong. Cheers!
Comment · 7 years ago
AMD’s primary advertised improvement here is the use of a TAGE predictor, although it is only used for non-L1 fetches. This might not sound too impressive: AMD is still using a hashed perceptron prefetch engine for L1 fetches, which is going to be as many fetches as possible, but the TAGE L2 branch predictor uses additional tagging to enable longer branch histories for better prediction pathways. This becomes more important for the L2 prefetches and beyond, with the hashed perceptron preferred for short prefetches in the L1 based on power.

I found this paragraph confusing, is it talking about data prefetchers (Which would make sense b/c of the mention of short prefetches) or branch predictors? (Which would make sense b/c of the mention of TAGE and Perceptron)

Comment · 8 years ago
Does anyone know where I could get more information on Tools?
Comment · 8 years ago
Comment · 8 years ago
Comment · 9 years ago
I was under the impression that the previous discussion got flagged because it was behind a paywall.

Don't despair, I think we do care. :)

Comment · 9 years ago
Neural networks aside, machine learning is often used for implementing prediction mechanisms in CPUs. Good examples of prediction mechanisms are:

- Branch Predictor

- Cache Replacement Policy

- Memory Prefetcher

- Schedulers

Comment · 9 years ago
They mentioned in the article that the full cache of each die is available. Additionally, EPYC uses the same dies used in Ryzen. I'd look at earlier articles for Ryzen to determine latencies within a single die.

So for whatever cores are enabled on each die, you get the L1/L2 caches for each core as per the Ryzen launch. Additionally, you get all of the shared L3 cache, irrespective of the number of cores disabled per core complex. This pattern follows across all four dies in each socket.

Comment · 9 years ago
Even when discussing CPU caches, there are policies that can severely outperform LRU, specifically at the Last-Level Cache (LLC).

LLCs often are exposed to access streams where the temporal locality (which is the assumption that makes LRU good) has been filtered out by earlier caches.

For that reason, newer cache replacement policies such as RRIP, SHiP, and Hawkeye have significant headroom to improve upon LRU (and PseudoLRU).

Comment · 9 years ago
WiFi Direct differs from WiFi Awareness in respect to the presence of the access point. In WiFi direct, there is no access point, and the devices connect directly to each other. With WiFi Awareness, an access point serves as a middle-man, but it is not necessary to access the Internet.
Comment · 9 years ago
I think parametric design could be used here, but to what extent that would be useful, I'm not sure.

Live from the official Hacker News API

A modern reader for Hacker News · SvelteKit + Skeleton