_mouvantsillage
Joined 7 years ago
Karma
129
Submissions
31
Member since
Dec 1
Recent submissions
Comment · 4 years ago
Comment · 4 years ago
Because Jupyter originates from the IPython project, hence the ipynb (IPython NoteBook) extension.
IPython initially was a monolithic project that offered the notebook interface and the Python kernel in a single release. When the notebook interface was moved to a separate project, I suppose they kept the file extension for backwards compatibility.
Comment · 5 years ago
Changing username is allowed. You just need to ask by e-mail (see https://news.ycombinator.com/newsfaq.html).
I did it a few weeks ago and the change was effective a few hours later.
Comment · 5 years ago
Now I think I understand what you mean.
For many hardware engineers, I think that the message-passing semantics is a conceptual framework for explaining how simulators work. It is considered as a "necessary evil" that must be taken into account when writing HDL code.
When I write VHDL, I don't think in terms of communicating processes. I think in terms of combinational and sequential circuits that I describe with processes. The description is written in a way that makes the synthesizer generate the hardware that I had in mind.
I see a possible explanation for this mindset: since only a subset of VHDL or Verilog is actually synthesizable, we cannot rely only on the language semantics to write code that will map to functional hardware.
Comment · 5 years ago
While simulation is a well-established practice among digital hardware developers, I have the impression that formal verification is still largely ignored.
I hope it changes as free tools are emerging such as SymbiYosys https://symbiyosys.readthedocs.io
While this is still a long-term goal, I am planning to experiment how formal verification can be used in Racket-based hardware tools.
Comment · 5 years ago
All diagrams were created with Inkscape.
Comment · 5 years ago
My experience in the lower-level aspects of hardware synthesis is limited but I would love to explore this topic.
I use proprietary synthesis tools for FPGAs everyday but I do not develop them. My situation is similar to that of a software engineer who uses compilers and who could only explain how they work in general terms.
Comment · 5 years ago
In the "signal-of-vectors vs vector-of-signals" comparison, "vector" refers to the Racket data type used for arrays.
It should not be confused with "bit vectors", which are represented as integers (assuming that a bit can only be 0 or 1).
While it is theoretically feasible, I would rather not use an array to store bits.
I think that your question assumes a model of computation similar to VHDL or Verilog. The techniques I use in Racket are similar to those used in Clash ( https://clash-lang.org/ ) In VHDL or Verilog, signals are updated in reaction to events. In Racket, I implement signals as lazy data streams: values are "pulled" from signals, which can trigger the evaluation of other signals. This is possible because I restrict my models to synchronous circuits with a single clock domain.
You can read more about it in this post: http://guillaume.baierouge.fr/2021/03/14/simulating-digital-...
Comment · 5 years ago
Author here.
This post is part of an ongoing experiment to use Racket as a platform for hardware description languages. Describing a RISC-V core in Racket is a step in this direction, but the ultimate goal is neither to use Racket itself as an HDL, nor to define an embedded hardware description DSL in Racket. The long-term goal is to create an HDL that would benefit from Racket's "language-oriented programming" facilities, with the ability to simulate digital hardware, but also to generate standard Verilog or VHDL.
Comment · 6 years ago
I thing it was Borland Turbo C++ 3.0 for MS-DOS.
It had syntax highlighting, integrated help with full language and API documentation. Which was useful because I didn't have Internet access back then, at the beginning of the 1990's.
I had to buy a new PC with an Intel 386 CPU, and add "extended memory" to run the IDE. It couldn't run with only 640 Ko of RAM.
Comment · 6 years ago
I am the author of the question at stackoverflow.
The racket topic on SO does not seem very active, so I thought I could get answers here as well.
I have been developing it since 2009 and I think it has become a nice and fun tool to use, but not always easy.
From the "About" section (http://sozi.guide/en/about-sozi.html):
Sozi is a piece of software for creating animated presentations. It is generally used to make visual aids for lectures or meetings. With Sozi, a presentation is not organized as a sequence of slides, but rather as a succession of viewpoints on a map that you explore. Sozi is quite versatile. Some creators have already used it for other purposes, for example to make animated infographics, websites, or interactive fiction.