DHaldane

It's ok to build a compiler sometimes -- it's just very important to make that choice intentionally

This is an old story, rehashed without new information.

That 7nm chip from SMIC is what prompted the export controls -- nobody thought they were close before that.

I've found the same thing - a little syntax example, some counter examples and generative AI does well generating syntactically correct code for PCB design.

A lot of the netlists are electrically nonsense when it's doing synthesis for me. Have you found otherwise?

I've found that for speeding up design generation like that, most of the utility comes from the coding approach.

AI can't do it itself (yet), and having it call the higher level functions doesn't save that much time...

I promise that we want to stay a software company that helps people design things!

Adding Skynetn't to company charter...

Agree that PDF digesting was the most useful.

I think Gemini could definitely do that microphone study. Good test case! I remember spending 8 hours on DigiKey in the bad old times, looking for an audio jack that was 0.5mm shorter.

I doubt it too, but I notice that I keep underestimating the models.

Do you have a challenge task I can try? What's the easiest thing I could get an LLM to do for circuit board design that would surprise you?

My gut agrees with you that LLMs shouldn't do this well on a specialty domain.

But I think there's also the bitter lesson to be learned here: many times people say LLMs won't do well on a task, they are often surprised either immediately or a few months later.

Overall not sure what to expect, but fine tuning experiments would be interesting regardless.

Update: Sonnet 3.5 is better than any other model for the circuit design and part finding tasks. Going to iterate a bit on the prompts to see how much I can push the new model on performance.

Figures that any article written on LLM limits is immediately out of date. I'll write an update piece to summarize new findings.

It really depends on the type of question, but generally I'm between Gemini and Claude these days for most things.

That's an interesting question - I'll take a few pokes at it now to see if there's improvement.

I'll note that the bandwidth doubled from PCIe 4.0 to PCIe 5.0 (it's now 30GHz).

Dealing with that speed increase is causing a whole lot of problems for all the designers in the ecosystem. It's a bit of a nightmare, but people are for sure using it (in your laptops, in the data center).

We ended up adding some specific features/strategies to the autorouter we're building for to handle those speed. It was pretty hard to get right.