Comment Comment by brucehoult And all modern high performance Arm and x86 cores do more fusion than RISC-V cores that are currently on the market.Intel has being fusing `CMP` and `Bcc` since Core 2 and AMD since Zen 1.This is- already one instruction in RISC-V- an *extremely* common pattern, often occurring once every 5 or 6 instructions. parent brucehoult 2 months ago
Intel has being fusing `CMP` and `Bcc` since Core 2 and AMD since Zen 1.
This is
- already one instruction in RISC-V
- an *extremely* common pattern, often occurring once every 5 or 6 instructions.