brucehoult

Or Mojo, recently acquired by Qualcomm, and even more recently fully open-sourced under Apache 2 license.

That's how it works, yes, if the originator makes it freely available then so does ISO.

The 256 byte hardware stack is plenty for function return addresses and temporary use within a function. How deep are you planning to nest function calls anyway?

You can create as many other stacks as you want using pairs of Zero Page locations as stack pointers.

Best practice for recursive/reentrant code (e.g. compiling C) is to follow modern RISC/x86_64 practice and reserve a few (16 maybe) Zero Page locations as argument/working registers, a few (16 maybe) as callee-save registers, and have prolog and epilog utility functions that create/destroy a stack frame and save/restore N bytes of callee-save ZP locations.

You can unroll those into a sequence of elements like...

    lda $1F
    dey
    sta (SP),y
    lda $1E
    dey
    sta (SP),y
    :
    lda $10
    dey
    sta (SP),y

... at 5 bytes and 11 cycles per byte saved. And of course jump into the appropriate part of the sequence.

> I still prefer programming the Z80 over the 6502 though :)

I really don't.

There are some few things you can fit into and get working fast in the Z80's A + 6 registers (IX and IY are not useful if speed is the aim), but for anything complicated the 6502's 256 Zero page locations — any pair of which can hold a pointer you can index off — is far superior.

The Z80 is awful at accessing memory for anything other than a simple absolute address or sequential access or push/pop of a register pair. It's better for manipulating 16 bit values, but not as much as you'd think especially once you run out of three register pairs plus ToS.

Also I haven't looked closely but I don't know if you could find space to fit it in the remaining Aarch64 encoding space.

The existing a64 conditional branch instructions use a 19 bit field to hold the offset. Add two registers to compare (10 bits) and 3 bits to choose between EQ, NE, LT, LTU, GE, GEU and you're already at 32 bits before having an "opcode" field to choose "RISC-V style conditional branch".

Of course you could reduce the branch offset size down to RISC-V's ±4k which only needs 11 bits when you only have 4 byte instructions, but that's still a 24 bit chunk of unused opcode space to find.

Oh .. looks like 0b10xx is still completely unused. We could grab maybe 1/4 of it

So could do ...

    [31:28] (4 bits):  0b1000 (Fixed primary opcode .. or 0b1001, 0b1010, 0b1011)
    [27:23] (5 bits):  Rs1
    [22:18] (5 bits):  Rs2
    [17:15] (3 bits):  Cond (EQ, NE, LT, GE, LTU, GEU, + possible 2 more)
    [14:4]  (11 bits): Offset (Signed ±4k PC-relative offset)
    [3:0]   (4 bits):  0b0000 (Fixed minor opcode/extension identifier)

One problem here is this doesn't allow both 32 bit and 64 bit compares. And also the Rs1 and Rs2 are not in the usual places.

Maybe...

    [31:28] (4 bits): 0b1000 (Fixed primary opcode)
    [27:21] (7 bits): Offset[12:6]
    [20:16] (5 bits): Rm
    [15:13] (3 bits): Cond (EQ, NE, LT, GE, LTU, GEU, etc)
    [12:10] (3 bits): Offset[5:3]
    [9:5]   (5 bits): Rn
    [4:2]   (3 bits): Offset[2:0]
    [1]     (1 bit):  sf (Size flag: 0 = 32-bit compare, 1 = 64-bit compare)
    [0]     (1 bit):  0b0 (Fixed)

I think this fits other instruction formats better .. and gives a ±16k branch range.

Some ::coff:: would criticise the split up offset field. Not RISC-V fans of course. And this puts sf in a non-standard place.

Some more playing around is needed .. over to you Arm.

SVE2 is compulsory in ARMv9-A, but NEON is optional?

C-Sky and Andes NDS32 were popular enough to be supported by both GCC and the Linux kernel, both switched to RISC-V. ESP32 switched to RISC_V for all new chips.

Interestingly Synopsys's ARC's latest version ARC-V is RISC-V.

I think all major FPGA vendors now offer fully supported RISC-V soft cores either alongside their older proprietary ISAs or as the latest upgrade. Several (e.g. Microchip and Gowin) have included real RISC-V cores inside FPGAs.

Why? It'll still run fine.

Just like Debian still runs on original x86-64-v1 from 1999, not x86-64-v3 (needs AVX2,FMA, BMI1, BMI2, LZCNT) or even x86-64-v3 (needs AVX-512).

Similarly, Debian for arm64 still requires only ARMv8.0-A from 2011 not even ARMv8.2-A (everything from A75/A55 to A78/N1/V1) let alone ARMv9-A (A710, A510, X2 and on).

Why would they do in the RISC-V world what they totally haven't done in amd64 or arm64?

Not me for sure. I have no idea about you. Of household name companies I've only worked at Mozilla and Samsung R&D. And SiFive if you count people in threads such as this.

I could of course be wrong but I think the publicly known history sets the pattern pretty reliably for the speculation.

Such as?

There is still plenty of unused 32 bit (30 bit) opcode space.

I specified "popular 64 bit ISA", which comes down to amd64 and arm64. But you can include Elbrus and LoongArch if you want. Or POWER. Or Itanium.

> I assembly by hand almost any function that is not too simple I can make it shorter on Cortex-M33 than on RISC-V

Not if you use the RISC-V ISA properly.