Previously we were using flip chip where silicon was exposed. With backside power delivery, there's now wiring on both sides of the chip. The transistors are buried. The article discusses how debugging is harder since nothing is exposed, and how there's now more thermal resistance.
Intel's implementation has other factors, as discussed in the Anandtech article. Normally there's a fairly thick silicon base underneath the transistor layer, but Intel polishes that away to nearly nothing after the frontside signal wire layers are put down (to make hooking up the backside power easier). That greatly reduced structural strength & is a somewhat taxing process, so before doing the polishing down, they put a carrier wafer atop the frontside signal wire layers, adding some structural strength. And there it stays.
Which means now that the top of the chip has a carrier wafer just for structure. Then the signal wire layers. Then the transistor layer with a bunch of PowerVias also in it. Then the backside power layer.
In the first sample chip, there's still a quite a few signal layers, 14, Vs 15 on other chips. Only down by 1. But better chip utilization and other benefits (ir droop). The backside is 4 layer. Maybe maybe the backside power delivery might have (or maybe could someday) greatly let them cut down on the number of wire layers, which are all now between the transistors & the heatsink. But not yet. So there's a significant number of layers of things burying the transistors now.
None the less, the thermals here looked fine.
It's a great article.
Intel's implementation has other factors, as discussed in the Anandtech article. Normally there's a fairly thick silicon base underneath the transistor layer, but Intel polishes that away to nearly nothing after the frontside signal wire layers are put down (to make hooking up the backside power easier). That greatly reduced structural strength & is a somewhat taxing process, so before doing the polishing down, they put a carrier wafer atop the frontside signal wire layers, adding some structural strength. And there it stays.
Which means now that the top of the chip has a carrier wafer just for structure. Then the signal wire layers. Then the transistor layer with a bunch of PowerVias also in it. Then the backside power layer.
In the first sample chip, there's still a quite a few signal layers, 14, Vs 15 on other chips. Only down by 1. But better chip utilization and other benefits (ir droop). The backside is 4 layer. Maybe maybe the backside power delivery might have (or maybe could someday) greatly let them cut down on the number of wire layers, which are all now between the transistors & the heatsink. But not yet. So there's a significant number of layers of things burying the transistors now.
None the less, the thermals here looked fine.
It's a great article.