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Comment by IshKebab

> a complete CI on our chip took 4 days

So rather than just say "ok we won't do simulations of the full chip in CI; we'll just do module testbenches which are much quicker" you scrapped the whole thing?

> Version control sucks unless your data is text--generally that's only your Verilog.

So you don't use version control because it "only" works with the most important things in your repo?

> Tcl is a decent enough language

Sure, compared to Bash or BASIC or other ancient terrible languages. It's pretty terrible compared to any vaguely good language. Even PHP or 90s JavaScript are leagues better.

>the stuff you write is no more than a one off and the real product is your chip--so nobody is going to reward you for a "good" script in any language.

Yeah I've heard this from people at my company too. So do you really completely throw away your entire infrastructure and start from scratch for every chip? If not it's hardly a "one off". And yes, people are going to reward you - your future selves will say "thank god you didn't choose to use such a bug prone language that I spend all my time fixing basic type errors".

> I've seen more verification in hardware before shipping a product than I EVER have seen in any software role.

For obvious reasons. Chips are much simpler than software and therefore way easier to verify, and missed bugs are extraordinarily expensive. I bet FPGAs don't get as much verification.

Your post is exactly the sort of attitude I was talking about - thanks for the demonstration!

parent IshKebab 4 years ago

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