In chip design, there are a lot of non-software people who have been burned by software people. Given the amounts of money flying around, there are always a lot of charlatans looking to take a chunk out of you.
We used to do CI--a complete CI on our chip took 4 days. The library took 3 weeks to go through CI. Version control sucks unless your data is text--generally that's only your Verilog. Tcl is a decent enough language--the problem is that the stuff you write is no more than a one off and the real product is your chip--so nobody is going to reward you for a "good" script in any language. SystemVerilog wasn't meant to be a good language--it's an EDA vendor lockin meant to extract maximal money from hardware people.
And I've seen more verification in hardware before shipping a product than I EVER have seen in any software role. Yes, even those with "good" testing.
In chip design, there are a lot of non-software people who have been burned by software people. Given the amounts of money flying around, there are always a lot of charlatans looking to take a chunk out of you.
We used to do CI--a complete CI on our chip took 4 days. The library took 3 weeks to go through CI. Version control sucks unless your data is text--generally that's only your Verilog. Tcl is a decent enough language--the problem is that the stuff you write is no more than a one off and the real product is your chip--so nobody is going to reward you for a "good" script in any language. SystemVerilog wasn't meant to be a good language--it's an EDA vendor lockin meant to extract maximal money from hardware people.
And I've seen more verification in hardware before shipping a product than I EVER have seen in any software role. Yes, even those with "good" testing.