> Executing more instructions for a (really) common operation doesn't mean an ISA is somehow better designed or "more RISC", it means it executes more instructions.
True. But as bonzini points out (or rather, hints at) in https://news.ycombinator.com/item?id=24958644, the really common operation for array indexing is inside a counted loop, and there the compiler will optimize the address computation and not shift-and-add on every iteration.
See https://gcc.godbolt.org/z/x5Mr66 for an example:
for (int i = 0; i < n; i++) {
sum += p[i];
}
compiles to a four-instruction loop on x86-64 (if you convince GCC not to unroll the loop):
.L3:
addsd xmm0, QWORD PTR [rdi]
add rdi, 8
cmp rax, rdi
jne .L3
and also to a four-instruction loop on RISC-V:
.L3:
fld fa5,0(a0)
addi a0,a0,8
fadd.d fa0,fa0,fa5
bne a5,a0,.L3
This isn't a complete refutation of the author's point, but it does mitigate the impact somewhat.
True. But as bonzini points out (or rather, hints at) in https://news.ycombinator.com/item?id=24958644, the really common operation for array indexing is inside a counted loop, and there the compiler will optimize the address computation and not shift-and-add on every iteration.
See https://gcc.godbolt.org/z/x5Mr66 for an example:
compiles to a four-instruction loop on x86-64 (if you convince GCC not to unroll the loop): and also to a four-instruction loop on RISC-V: This isn't a complete refutation of the author's point, but it does mitigate the impact somewhat.