>[She] complains Risc-V need 4 instructions to do what x86_64 and arm does in two, but... it says Risc-V.
So… what, it should take 5 instructions?
Executing more instructions for a (really) common operation doesn't mean an ISA is somehow better designed or "more RISC", it means it executes more instructions.
>And x86_64 CISC instructions devolve to a pile of microcode anyway.
Some people seem to have this impression that like every x86 instruction is implemented in microcode (very, very few of them are) and even charitably interpreting that as "decodes to multiple uops" (which is completely different) is still not right. The mov in the example is 1 uop.
So… what, it should take 5 instructions?
Executing more instructions for a (really) common operation doesn't mean an ISA is somehow better designed or "more RISC", it means it executes more instructions.
>And x86_64 CISC instructions devolve to a pile of microcode anyway.
Some people seem to have this impression that like every x86 instruction is implemented in microcode (very, very few of them are) and even charitably interpreting that as "decodes to multiple uops" (which is completely different) is still not right. The mov in the example is 1 uop.