That's good in theory, but ... it's not realistic. The compilers are too unstable. I lost a couple days of my life last year because Quartus forgot how to route its multipliers.
But usually you only have to floor plan if you're near the limits of your target FPGA, or if you're using some of its special IP (like say pinning some of DRAMs or PLLs).
But usually you only have to floor plan if you're near the limits of your target FPGA, or if you're using some of its special IP (like say pinning some of DRAMs or PLLs).