IMHO, If you have to floor plan, you're doing it wrong.
You should try to design FPGAs so that they work like software, in that you should be able to run the tools consistently like you would software through a C compiler and not have difficulty with failed timing. If you had to do floor planning to close timing, you are giving up a huge advantage.
You should try to design FPGAs so that they work like software, in that you should be able to run the tools consistently like you would software through a C compiler and not have difficulty with failed timing. If you had to do floor planning to close timing, you are giving up a huge advantage.