xirbeosbwo1234

That's not quite accurate. Every core has access to the entire L3, including the L3 on an entirely different socket. CPUs communicate through caches, so if a core just plain couldn't talk to another core's cache then cache coherency algorithms wouldn't work. Though a core can access the entire cache, the latency is higher when going off-die. It is really high when going to another socket.

The first generation of Epyc had a complicated hierarchy that made latency quite hard to predict, but the new architecture is simpler. A CPU can talk to a cache in the same package but on a different die with reasonably low latency.

(I don't have numbers. Still reading.)

First off, it's not a direct comparison. The Epyc has one L3 cache per chiplet. This means that latency is not uniform across the entire L3 cache. This was a serious concern on the first generation of Epyc, where accessing L3 could take anywhere from zero to three hops across an internal network. AMD has greatly improved the problem on the more recent generations by switching to a star topology with more predictable latency.

That said, there are two major reasons:

1. Epyc is on a chiplet architecture. Large chips are harder to make than small ones. Building two 200mm^2 chips is cheaper than building one 400mm^2 chip. Since Epyc has a chiplet architecture, this means they can put more silicon into a chip for the same price. This means that Epyc can be just plain bigger than the competition. This comes with some complexity and inefficiency but has, so far, paid off in spades for them.

2. Epyc is on a newer process. This means AMD can fit more transistors even with the same area. Intel has had serious problems with their newer processes, so this is not an advantage AMD expected to have when designing the part. The use of a cutting-edge process was, in part, enabled by the chiplet architecture. It is possible to fabricate several small chips on a 7nm process even though one large chip would be prohibitively expensive, and AMD has been able to use a 14nm process in parts of the CPU that wouldn't benefit from a 7nm process to cut costs.

The first point is serious cleverness on the part of AMD. The second point is mostly that Intel dropped the ball.

>Tesla is leagues ahead if I’m not mistaken

You are. Pretty much every other manufacturer offers adaptive cruise control, lane keeping, and the like. They're just honest about their capabilities.

It's a shame that the necessary work of criticizing our media is so often undertaken dishonestly.

>When Donald Trump made the same calculation, saying he couldn’t cut ties

This is not what happened.

Donald Trump denied that the Saudi royalty was known to be behind the murder of Khashoggi despite the conclusions of U.S. intelligence. He was part of the coverup, obscuring the known facts to preserve his relationship with bin Salman. Joe Biden, on the other hand, said bin Salman was responsible for his murder but decided not to penalize him.

Both of those decisions are unacceptable to me. That does not make them the same.

Say what you will about the New York Times, but they rarely tell lies as brazenly as Mr. Taibbi.

I certainly question the orthodox view that software should be fault-tolerant and horizontally-scalable. If programmer time is more valuable than machine time, then why can't my team get a single server with a few TiB of RAM and a few hundred cores and forget all the gnarly problems of distributed computing? Why do we accept that our hardware is unrelaible and then spend so much effort making our software tolerate failure?

I do not know whether or not mainframes are the right solution, though. I don't really know anything about them. I don't know whether or not the architecture is the correct approach.

>IBM has grown usage as measured by MIPS, a method of calculating the raw speed used, by 350% over the past ten years.

That's an awful metric. MIPS isn't even a good way of measuring aggregate performance and aggregate performance is a terrible way of measuring adoption.