mysterion1

Judging by the register area bit density, it seems it would have space for 3-5kbit SRAM cache (replacing the 26,368 bit ROM). I wonder if the basic 4 ops+some approximation functions like sqrt would fit in there. Purely alternative history ;)

Wouldn't it be simpler for Intel to have designed a chip, with those 8 identical instructions (xfer, shift, add, arith, far jmp, far call, local jmp, misc), but read/executed from normal RAM accessible by the user, perhaps with a tiny cache, instead all these ROM/microcode special compression/hidden architecture shenanigans?