mallets
Joined 7 years ago
Joined 7 years ago
Sipeed teased a similar hack using some (undisclosed) USB-wifi chip, though I don't take them seriously as none can get their hands on the chips they tend to use.
Many cheap USB 3 Wifi 5/6 dongles out there, based on RTL8852BU and such. Just one QFN IC and XO. Their "firmware" seems to be a binary blob loaded over USB. I'm skeptical that these "testmodes" can be figured out with just bruteforcing, wonder if they load custom firmware for compliance testing or just leave those routines hanging around in release firmware too.
Closed binaries aren't much of a deterrent these days, we might see more such "discoveries" for a lot of devices.
On a technical note, not much I can find about the signal quality. Phase noise, images, DC Offset, etc. Have to get my hands on one, ESP32-S31 seems promising.
Liberals and progressives don't agree on most things related to (free) trade, but agree on not "bullying" allies for no reason and little profit.
As I mostly deal with single channel applications, I get to use double superhet and avoid runtime calibration. Not an option here, Zero-IF has too much in the Pros column for multichannel.
I have very little experience with MIMO / phased-arrays, this application likely doesn't need ultra high SFDR.
Neat way to reduce cost and pin-count? But I think the typical FPGA clock tree has poor jitter performance. Not using the internal PLL(s) might help with spurs but the clock buffers are unavoidable.
The documentation mentions it's likely further degraded by noise from switching regulators. Oh the joys of hunting RF noise sources.