jevinskie
Joined 16 years ago
Joined 16 years ago
https://github.com/caradoc-org/caradoc
http://spw16.langsec.org/slides/guillaume-endignoux-slides.p...
Just wonder - why are EDA tools just now starting to get HiDPI support? I’m pretty sure Altera, Xilinx/AMD, etc haven’t bought HiDPI monitors for their own developers!
My back burner project for them is to create a PCIe TLP sniffer/MiTM/device emulator by hooking up two together via 10 GbE for relaying TLPs with one of the remaining 10 GbE connection going to a host PC for the sniffed/injected TLPs. The Aria 10 FPGA PCIe hard IP allows for either root or endpoint mode so I “just” need to draw the rest of the owl, avoiding any Quartus IP modules that would make the setup non-transparent.
I’m not sure what using a 10 Gbit link for PCIe will be like with faster devices but fail0verflow got away with TLP proxying with 115200 baud UART. [1]
[0]: https://www.ebay.com/itm/335904285904 [1]: https://fail0verflow.com/media/33c3-slides/#/11
If you like FT2232, you’ll love the Tigard board that takes a FT2232H and adds level shifters and is basically as tricked out as you can make a FTDI adapter. https://github.com/tigard-tools/tigard
https://gist.github.com/jevinskie/58c65760a0b54f117a8d0f3b32...
edit: CPA_ACC_SVC_TYPE_XML https://github.com/ravynsoft/ravynos/blob/ee81203faa28ab3e6a...
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