enzo05814648

Sorry to be pedantic but...every "boolean" logic gate can be made out of NAND gates pretty trivially (XOR too for that matter). So you just have to design a computer from logic gates and then decompose each one into NANDs.

"I made a computer out of n logic gates" doesn't sound as cool I guess?

Granted I am criticizing the concept and post title, not the execution.

They frame this as fraud-prevention but I don't really buy it.

I think of I this way. As a casual/hobbyist user, maybe I'm happy to accept a 10% risk of the device failing prematurely in exchange for saving $20 on a memory upgrade. Ok, so these unscrupulous sellers will never tell me that info up-front...but this defective-by-design system doesn't help me either. The sellers playing this shady game might not accept returns (one example of this already in the github issue linked from the main thread) and there's no sign anything's wrong until you receive and boot up. So the user is left holding the bag, with kneecapped memory capacity, and the same stability risks anyway!

If these DRAM-upgraders are really so clever, they'll find a way to bypass this (patched firmware or hacked serial in the CPU). At least, it'll work until the user is out of the 30-day period when they finally update the firmware.

Or if the CPU/mainboard can really detect this in a non-defeatable manner, why cut the usable memory? Just print something to dmesg or stderr when the user logs in. "This device's memory has been modified and may be unstable, warranty blah blah"

Apple locks down fingerprint/camera module swaps, but at least there's a plausible (afaik) security rationale for it. Seems like Raspberry just got tired of being undercut on price.

I get the "skip intro" / "skip credits" prompts while watching on Infuse, so yes it's possible, but it's specific to only certain shows (probably those with properly-titled chapters). I'm also not sure if the prompts appear in other clients; Infuse might have implemented it from scratch using the chapter titles.

Nice board, looking forward to seeing your next one. A little feedback, helpful I hope:

A "via" is basically just a wire stuck right through the whole board top-to-bottom. (Okay, it's not really a wire. They drill a hole and then chemically grow a layer of copper that fills the hole.) You can connect the copper pattern on any layer(s) to that "wire", so it's often used to route a signal from one layer to the other. But you already have a real wire going through the board: the GND header pin! So no via is necessary; just connect directly to that pin on each layer (kicad probably did this for you automatically). This trick works with all thru-hole pins.

For RF or high-current applications, sometimes you cover a board with a grid of vias, just making redundant connections between the planes all over the place, "stitching" them together. But careful, add too many vias and the PCB shop will bill you extra.

Putting a GND pour on the top layer is a good idea. It's lower-impedance than individual skinny traces, and takes less/zero effort to route. The GND trace you manually routed isn't necessary; you can see by the transparent-red shape that kicad already has copper there. However, you ended up with a little "island" of dead copper between R2 and C2, which is the real reason you needed the via.

A better approach would be to use the bottom layer for +3.3V power instead of a redundant ground pour. This gets rid of the +3.3V traces (BTW, best to use a single, thicker one instead of 2x side-by-side) and unifies the island into the ground pour. Even though this is a micro-power application, playing the traveling-salesman game with long scraggly power traces is never a good idea. You would still need vias to connect each top-layer +3.3V SMD pad to the bottom-layer power plane, but the signal-integrity benefits of a plane make this worth it. Maybe the absolute best is an uninterrupted GND plane on the bottom and a +3.3V pour on the top.

Putting SMDs on the bottom side makes the board cost more, so good call leaving them all on top, but putting traces on the bottom layer is free. So you can even move signal traces between layers to avoid cutting up your planes too much. It's "fun" with big complex boards, like untying a giant knot...

You are very miserly with your +3.3V global net symbols in the schematic! You can place as many as you want to optimize the schematic's readability. Especially near the CSB pin, the 4-way solder dot looks like some intermediate signal in a voltage divider, but it's actually just +3.3V. Same suggestion with GND -- basically, it's more informative to read "this pin is GND, and this pin is GND" than "these two pins are connected, I wonder what they're doing...oh, it's all GND".

Pull-up resistors are usually oriented vertically, too, so they graphically pull "up"!

Anyway...I hope you don't mind all my constructive criticism. It's nice to see something on HN I know about!