blp
Joined 11 years ago
Joined 11 years ago
Has nice models and details on post cmos, for the curious. The papers (nikonov and young) are excellent, though I think they underrate the back end scaling challenges.
This is about replacing the low k dielectric in the backend, and makes sense if you consider that backend metal will move to W or Co. so long as this is CMP capable (maybe?) this makes sense.
Who are you optimizing for?
If you are building enterprise software, vs hardware, vs consumer products...the process can be very different, with different balances on risk and very different timelines
It would be better to use logic density, but it is easier to use numbers we are used to.
To figure this out, draw a square, and each node is an exposure.
This process works forever in theory, but is limited in practice by the mutual registration of the exposures.
In Huangs law, si is commoditized, so the benefit accrues to the designer and software makers, and really only in narrow domains.