akuma73

A lot of ex-Alpha engineers went to PA-Semi which Apple then acquired. Those people are responsible for the epic custom Apple ARM CPUs.

This isn't totally surprising.

x86 vs. ARM/RISC-V has fewer registers which can mean more spill/fill to the stack which results in more instructions to do the same work.

The instruction decode length for x86 has been creeping up with 64-bit encodings and SIMD extenstion (prefix bytes) as you can see it's 3.96 for x86 vs. 4.00 for ARM.

Isn’t that a huge conflict of interest?

It’s hard to see how AMD would get capacity ahead of Intel CPUs.

Because of the initial conditions of the universe and the laws of physics. That's as deep as we can go right now.

They should drop their custom ASICs and just stick a Qualcomm Snapdragon as a replacement. They could use Android and create a platform with an app store with APIs to access their sensor. Opening up the hardware in this standard way to developers would really add a lot of value to their cameras.

I have no idea why they haven't done this already.

Fake news. These are not Macs and are very overclocked PCs (Hackintosh).

Apple also fully controls the hardware and software stack for both CPU and GPU.

What always confused me was that "its" is meant to denote possession. For example, I find this to be more consistent.

Bob's purpose vs. It's purpose

For consistency, shouldn't we use: Bobs purpose

The cortex m0/m3 CPUs most certainly do have breakpoints, svc (trap), interrupts and an optional memory protection unit.

The Atmel CPU is more constrained but still has hardware breakpoints, IO instructions, watchdog timers and interrupt support. It also has far more complex addressing modes (more CISC-y) to save on instruction counts and a variable length instruction set encoding where memory space to store code is a first order concern.

I’m also sure there is a memory controller to control the SRAM.

So, even if you were to build a simple micro controller, you’d need a lot more features and most likely higher performance (and power efficiency) than you would get from a trivial 2-stage pipeline. Not to mention there are no instruction or data caches in this RISC-V machine.

Sorry to burst any bubbles here, but this is s very incomplete implementation.

You couldn’t run anything but small toy programs on this machine. This is more like what a student would build in an undergraduate course in computer architecture.

For example, there is no MMU, no debug support, no traps, no interrupts, no exception handling, no OS privledge levels, no FP, no memory controller etc.

Of course, one wouldn’t implement all of these in a few hours.

The fact that this is RISCV is somewhat of a red herring as you could do a similar thing with a restricted subset of MIPS or ARM or even x86 as they do in UT Austin’s comp arch class.

Have you heard of Amdahl’s law?