__init

I work remotely on a small-ish research team. Almost all of my immediate colleagues are in the US or Western Europe. Most (all?) of the folks on P- and E-Core Engineering that I work with are full employees (i.e. not contractors) in the US or Israel. I'm not sure I'd know if they were H1Bs, but they're generally very knowledgeable and hardworking. From my perspective, there's little outsourcing on the core businesses (pun fully intended).

As far as comp goes, mine is competitive with Bay Area FAANG.

No; in fact, we're doing more of our core development in the US than at some previous points in our history.

(I work at Intel, but this is just my personal observation.)

At Berkeley, course numbers >100 are upper-division, and those <100 are lower-division, introductory classes. Especially in the CS department, the upper-division courses are far from introductory. 61B is the the second in the 61A-B-C series, which is required for all CS majors. (A fourth lower-division class, CS 70 ("Discrete Mathematics and Probability"), is also required, but is independent of the 61 series.)

X11 forwarding for Cadence's chip layout tooling is practically unusable nowadays! Sub-1 FPS, even on a reasonable 1 Gbps pipe with only 3-4 ms ping. I had to use NoMachine when I was doing that work -- proprietary tooling that does the "simpler" image/video streaming.

(Disclaimer: I work at Intel, but not on server products. Opinions are my own.)

There's a lot more that goes into a server platform than just the cores, for instance: the BIOS code, the BMC support, the maturity of the motherboard designs, etc. These are all areas where Intel seems to still have an edge -- but I'm also very excited about our upcoming server architectures on the core/compute side.

Further optimization are certainly possible, especially as the hardware improves and gains additional capabilities. With regards to your suggestion, this is essentially what already happens, thanks to the magic of out-of-order cores.

Most assemblers for Intel syntax will let you write:

    add eax, [4]

if you desire. Indeed, many disassemblers will follow suit in unambiguous cases. IDA, for example, does this.

This is one of my favorite episodes. I always thought the thin veiling helped to demonstrate the absurdity of both situations -- perhaps it was even done intentionally for that reason.

Erm, I'm not sure if you're being sarcastic, but they certainly are not giving these away to youtubers. This is a >$1 million instrument that isn't even very useful for hobbyist electronics. The ones they give away are from their new EDU line that does around 100 MHz sampling.

More specifically, it's a system on a _package_. A TLB lives on the _die_, though, with one in each core.

> Real-world IPC is something like 3x (!) that of Intel right now - obviously it also clocks lower

That's the problem, though -- if you clock yourself much lower, of course you can get higher IPC; you can pack more into your critical paths.

Now, certainly Apple has some interesting and significant innovations over Intel here, but quoting IPC figures like that is highly misleading.