ZirconiumX
Joined 9 years ago
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Member since
Nov 17
Recent submissions
Comment · 3 months ago
Comment · 8 months ago
> Being female or male is a fact about the biological world.
I was responding to this line, which I feel marginalises intersex people and could have been more inclusively worded.
I apologise if my comment somehow seemed to defend LLMs having a biological sex, despite me having said nothing to that effect.
Comment · 8 months ago
You appear to have forgotten the existence of differences in sexual development (DSD).
The chart in [1] is a good visualisation of that, if you wish to learn more.
[1]: https://www.scientificamerican.com/article/beyond-xx-and-xy-...
Comment · 3 years ago
Sorry, I really don't see where the issue is.
Nothing forces you to use C++ scripting here; Yosys has a shell that you can enter commands in, and it takes via `-s` a file of commands; a script.
That the default scripts are written in C++ to not need dependencies does not mean you also need to write your scripts in C++.
Comment · 3 years ago
...is your bugbear here that these particular scripts are written in C++ instead of Python?
Yes, those flows use ScriptPass, because for the most part they are scripts. If they were written in Tcl, then Yosys would need to depend on a Tcl interpreter, and equivalently a Python interpreter for Python. By just using C++ for these scripts which usually only developers need to modify, Yosys does not need to depend on either.
But anyway, if I was going to mess about with the flow that much, I'd start by running `help synth_xilinx`, which outputs a list of all the commands that it calls (more or less; it can't model control flow like a proper language can), and then that can be edited into what I need it to do.
Comment · 3 years ago
Reading your answers, I've noticed that there appear to be some major misconceptions about Yosys and how it works: certainly, ABC is a core part of a standard synthesis flow, but Yosys is based around a series of passes that modify a common intermediate representation. That should mean if anything it is very easy to use only part of Yosys.
Obviously it'd be off-topic to try to discuss your particular needs and use-cases of Yosys here, so feel free to email me at [email protected].
Comment · 3 years ago
If you have any questions about nextpnr, feel free to email me at [email protected].
Comment · 3 years ago
Well, at least part of this comes down to the fact that we did not choose a scripting language today, but at least a decade ago where Tcl was dominant in EDA and Python would not have been taken seriously.
Comment · 3 years ago
> > full disclosure: I work for YosysHQ
> let me take this opportunity to ask a question about something that makes absolutely zero sense to me: why did yosys insist on sticking with tcl over some more modern/well-known/familiar scripting language? yes everyone has their favorite tcl scripts for vivado or intel or whatever but none of them are transferrable to yosys irrespective of that fact that yosys supports tcl.
First: PYosys exists as Python bindings for Yosys, so you can in fact use a more modern scripting language for this.
Second: even if the Tcl scripts are not transferrable, a lot of our users do still have Tcl experience, and that transfers if nothing else.
But personally? For a lot of tasks you don't need a scripting language. If you want to turn a set of Verilog files into a JSON to pass to nextpnr-ecp5, that's `yosys -p "synth_ecp5 -abc9 -top top -json design.json" *.v` and there is neither Tcl nor Python involved here.
> further more, why is yosys itself basically scripting of ABC and nextpnr and etc using cpp instead of again using just some reasonable scripting language to connect the pieces?
Yosys is not simply some scripting around ABC: you need to parse input files, store this in an intermediate representation (RTLIL), elaborate and monomorphise the input structure, perform optimisation and logic minimisation on it; you need to map large structures like memories, hard multipliers and carry chains (ABC can't do that), legalise flop types and only then can you pass the logic to ABC. Once you get that logic from ABC, you need to turn it into cells that tooling recognises.
That the "script passes" we have that most front-end users use are so simple is because the complex logic is packed into neat passes to call.
> > multi-electrostatic placer
> um why? dreamplace exists? https://github.com/limbo018/DREAMPlace
We're aware of DREAMPlace, however: DREAMPlace itself is for ASIC applications, so you'd want to use DREAMPlaceFPGA instead, which is...limited to a simplified Xilinx architecture or whatever partial FPGA Interchange Format support they have. We consider speed a feature, and having to deserialise the target device and netlist into FPGA Interchange Format in the hopes that DREAMPlaceFPGA can understand it is...not fast.
So instead we're working on our own multi-electrostatic placer which can more tightly integrate with nextpnr than something using DREAMPlace[FPGA] could.
Comment · 3 years ago
I should point out that even the F4PGA page [admits](https://f4pga.readthedocs.io/en/latest/how.html) that ECP5 and iCE40 support is done through nextpnr, rather than VPR.
(actually nextpnr has slowly-maturing support for Lattice MachXO{2,3}, Intel Cyclone V and Gowin parts too)
Comment · 3 years ago
full disclosure: I work for YosysHQ, who have an alternative open-source place-and-route program - [nextpnr](https://github.com/YosysHQ/nextpnr/) - and YosysHQ presently has [a grant](https://activities.esa.int/4000141380) from ESA on improving nextpnr.
to be blunt: nextpnr is what happens when you look at VPR as prior art and base every design decision around doing the opposite of VPR.
VPR is flexible, true: you can define an architecture description inside an XML file, but I view the VPR XML format to be poorly considered.
- commonly in an FPGA you will have "legality constraints" - for example, a block of LUTs cannot simultaneously be in carry-chain mode and act as LUT RAM. to produce a legal solution, all these constraints must be satisfied. to nextpnr this is [two basic](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....) [API calls](https://github.com/YosysHQ/nextpnr/blob/master/docs/archapi....). to vpr, you must [walk the architecture](https://github.com/verilog-to-routing/vtr-verilog-to-routing...) to discover and cache legal placement positions. - VPR often requires significantly more detail about an FPGA than is easy to provide; for example, [how switchboxes are laid out](https://docs.verilogtorouting.org/en/latest/arch/reference/#...), or [routing metal resistance/capacitance](https://docs.verilogtorouting.org/en/latest/arch/reference/#...). to nextpnr, routing is just nodes and edges on a graph.
Further, VPR's algorithms tend not to be designed with performance in mind; simulated annealing as a placement method does not scale well past the tens of thousands of LUTs, which is why nextpnr moved from full simulated annealing to [heterogenous analytic placement](https://ieeexplore.ieee.org/document/6339278), and recently we have been working on a [multi-electrostatic placer](https://dl.acm.org/doi/abs/10.1145/3489517.3530568); both significantly more scalable methods based on using mathematical optimisation methods to place things nearby.
Comment · 4 years ago
DIre SIlicon DeXtrously Concatenates 8 and 9 (for SysV). Jubilee[1] came up with that and it's a useful mnemonic.
Comment · 6 years ago
I asked whitequark about the name; it's named Glasgow because it's where the headquarters of FTDI are based, and the initial prototypes were intended to be an open-source serial adapter gateware before feature creep set in.
Comment · 6 years ago
Distributing GCC does.
Comment · 6 years ago
GOWIN's design is very similar to the ECP5 in architecture, but the bitstream formats are notably different.
https://www.gnu.org/licenses/license-list.html#FreeBSD