PyComfy
Joined 13 years ago
Karma
91
Submissions
29
Member since
Jun 25
Recent submissions
Comment · 3 years ago
Comment · 4 years ago
34yo here, got called a cheater constantly, even by "top" players. Despite using a slow sensitivity myself, i would say that slow/fast sensitivity or wrist/arm aiming doesn't matter; I have seen plenty of people being very efficient with each technique. Just use what you are the most comfortable with. Something specific that tremendously helped me is putting fingers on each side of the mouse to lift it a little, the mouse is no more touching the mousepad, only your fingers, that way i can stop moving much more precisely. You no more think about aiming with the mouse but with your hand. When i need a slower sensitivity, i just lift the mouse higher. In the past i was playing with a CRT monitor at 160hz, now i am playing with a IPS monitor at 144hz (LG 27gl850-b); i have seen no difference in performing at KovaaK aim trainer[1]. Something that actually made a difference is where the sensor is located under the mouse. More the sensor was toward the back of the mouse (toward the wrist), more my aim was degrading. I also once tried a vertical mouse (Trust GXT 144) and did my best score ever in tracking, it was like holding a pen.
Comment · 8 years ago
Comment · 8 years ago
Intel shall definitively be worried
Comment · 8 years ago
for linear algebra, may i add http://immersivemath.com/ila/index.html
Comment · 8 years ago
Comment · 8 years ago
Is it really? If we go back to the roots, lisp is made of what John McCarthy calls the Primary S-Functions which are atom, cons, car, cdr, and eq (a.k.a =).
Of these five, clojure only has two (atom and eq)
Comment · 8 years ago
Does Graal support tail call optimization? It has been announced for hotspot +10 years ago but still not implemented as today.
Comment · 8 years ago
ah sorry. i did
import dis
dis.dis("a = foo.bar(b)")
1 0 LOAD_NAME 0 (foo)
2 LOAD_ATTR 1 (bar)
4 LOAD_NAME 2 (b)
6 CALL_FUNCTION 1
8 STORE_NAME 3 (a)
10 LOAD_CONST 0 (None)
12 RETURN_VALUEComment · 8 years ago
Naive interpretation of the bytecode (not even pre-decoded, just a switch statement).
And almost everything is resolved in the dynamic environment. for example,
a = foo.bar(b)
ldict = locals()
ldict['a'] = ldict['foo'].__getattribute__('bar')(ldict['b'])Comment · 8 years ago
Interesting experiences beyond the command line are game development tools; Each iteration try to make the barrier between artists/content creators and programmers thinner.
Comment · 8 years ago
My dad knew someone who had a reinforcing steel bar stuck into the middle of his head; The bar entered is mouth and exited in the middle of the top of his skill. After that, the guy was noticeably smarter but also more irascible. My dad theory was that the healing of the brain raised the number of synapses and ridges[1] in the damaged part of the brain (which in this case was right between the two cerebral hemispheres). Albert Einstein's brain had four ridges instead of three.
[1] https://en.wikipedia.org/wiki/Gyrus
[2] https://en.wikipedia.org/wiki/Albert_Einstein%27s_brain#Newl...
Comment · 8 years ago
Qualcomm Falkor (ARMv8 AArch64) vs Intel Broadwell and Skylake
https://blog.cloudflare.com/arm-takes-wing/
Multicore AVX512 lowers the frequency
The Qualcomm CPU only has the 128-bit wide NEON SIMD, while Broadwell has 256-bit wide AVX2, and Skylake has 512-bit wide AVX-512. This explains the huge lead Skylake has over both in single core performance. In the all-cores benchmark the Skylake lead lessens, because it has to lower the clock speed when executing AVX-512 workloads. When executing AVX-512 on all cores, the base frequency goes down to just 1.4GHz---keep that in mind if you are mixing AVX-512 and other code.
Comment · 8 years ago
https://thehackernews.com/2017/02/bypass-aslr-browser-javasc...
http://www.cs.vu.nl/~herbertb/download/papers/anc_ndss17.pdf
XI. CONCLUSIONS
In this paper, we described how ASLR is fundamentally insecure on modern architectures. Our attack relies on the interplay between the MMU and the caches during virtual to physical address translation—core hardware behavior that is central to efficient code execution on modern CPUs. The underlying problem is that the complex nature of modern microarchitectures allows attackers with knowledge of the architecture to craft a carefully chosen series of memory accesses which manifest timing differences that disclose what memory is accessed where and to infer all the bits that make up the address. Unfortunately, these timing differences are fundamental and reflect the way caches optimize accesses in the memory hierarchy. The conclusion is that such caching behavior and strong address space randomization are mutually exclusive. Because of the importance of the caching hierarchy for the overall system performance, all fixes are likely to be too costly to be practical. Moreover, even if mitigations are possible in hardware, such as separate cache for page tables, the problems may well resurface in software. We hence recommend ASLR to no longer be trusted as a first line of defense against memory error attacks and for future defenses not to rely on it as a pivotal building block.
Comment · 8 years ago
I always understood it as this
Transpilation: text to text (eg: Scheme to C)
Compilation: anything to anything but usually it implies text to binary code
transpilation is compilation but compilation is not necessary transpilation (the all squares are rectangles but all rectangles ...)
Iconic yachts: On board Steve Jobs's Feadship superyacht Venus
https://www.boatinternational.com/yachts/editorial-features/...
Jobs died before it was finished.