201984
Joined 2 years ago
Joined 2 years ago
Atomics are necessary nowadays though.
It's rather suspicious to leave normal handwriting out of the study, and makes me suspect bad faith.
People with this attitude are why the drains in my apartment keep backing up and my landlord sends emails threatening to evict whoever's flushing things they shouldn't.
With RISC-V, multiple instruction workarounds are needed for all of the above, and those sequences are usually sequentially dependent ones so they can't be run in parallel. i.e. the insanity of loading a 64-bit value through repeated 12-bit immediates with shifts, using multiple instructions to compute branch offsets, and RVV needing setvli instructions everywhere due to not having opcode space to encode vector length/type.
AArch64 is better, but still has problems with limited opcode space when it comes to future extensions. They've had to make "start mode" and "end mode" for SME to save on opcode space, and future compromises will likely be necessary.
Such as? I can't think of anything it does better for high performance cores.
Sometimes, you need to tell the designers NO. Moving background images don't help people figure out what the weather is going to be.
local x = condition ? value_a : value b
local x = condition and value_a or value_b