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Comment by spatular

Here is more information from official site [1,4,5]:

- native "Elbrus" ISA or x86 ISA,

- Ebrus ISA is VLIW, can dispatch 23 operations per cycle (33 with SIMD), in-order execution,

- it's stated that x86 code translation + register allocation is done in HW, but later they write about a software translator and full-system emulator,

- 6 ALUs (all support integer operations, 4 can do FP),

- 256 x 84-bit register file,

- hardware support for loops, including pipelining,

- some kind of module for async mem preloading,

- speculative execution and branching predicates,

- "4S" model has 4 cores,

- 800 Mhz core clock,

- 64 KB L1, 128 KB L2, 8 MB L3 (shared between cores),

- 3 DDR3-1600 interfaces, ECC support,

- 3 x 12GBytes/s inter-CPU links, support for up to 4 sockets,

- 65nm process, 380 mm^2 die size, 986e6 transistors,

- software is based on Linux 2.6.33 and Debian 5.0 with more than 3000 packages.

There are some benchmarks for older chip model "2S" (overclocked to 500MHz, 2 cores) [2,3]. FP performance is about 1-5x of Pentium M 1GHz (1 core?) depending on benchmark, integer performance is about 1x. New CPU, "4S", should be 3 times faster than "2S".

[1] http://www.elbrus.ru/arhitektura_elbrus

[2] http://www.elbrus.ru/files/535269/9f0cd8/50606f/000000/2014-...

[3] http://www.elbrus.ru/files/535269/0e0cd8/50586f/000000/2014-...

[4] http://www.mcst.ru/mikroprocessor-elbrus4s

[5] http://www.mcst.ru/mikroprocessor-elbrus4s-gotov-k-serijnomu...

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Edit: loop pipeling, OS information

parent spatular 11 years ago

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