YZF,why can't we start from an optimized FPGA - i.e. small memory blocks spread all around with massive bandwidth and low latency, and find a way to give decent enough access to the cpu to all that memory ?
And yes i know that the cpu will be the bottleneck, but it will be the bottleneck anyway.
And yes i know that the cpu will be the bottleneck, but it will be the bottleneck anyway.