The moat of the closed source EDA tools is the validation hours that went into them.
I use the open source EDA tools for VLSI everyday and I do like them, especially how hackable they are, but they are very unreliable compared to the closed source tools, and that's not the highest bar.
Run time of the open source EDA tools are also very slow for designs over, say, ~250K gates. And that's an issue when in commercial designs the base unit for measuring the number of gates in a macro is megacells, i.e. 10^6 cells. Much of the effort of the commercial tools has just been keeping up with Moore's law which is not easy when many brute-force form EDA algorithms are like n^3 even with heuristics.
I use the open source EDA tools for VLSI everyday and I do like them, especially how hackable they are, but they are very unreliable compared to the closed source tools, and that's not the highest bar.
Run time of the open source EDA tools are also very slow for designs over, say, ~250K gates. And that's an issue when in commercial designs the base unit for measuring the number of gates in a macro is megacells, i.e. 10^6 cells. Much of the effort of the commercial tools has just been keeping up with Moore's law which is not easy when many brute-force form EDA algorithms are like n^3 even with heuristics.