It will be, I'm just not happy with my blog post before making it live. The blog will have a live interactive chat and a link to the repo with the HDL.
I don't think anything I did was particularly novel, as I really just wanted to see how fast I could push a commodity FPGA to it's limit.
Scaling to an ASIC or getting into the billions of params is where the real engineering is! This was just a side project for a side project for me while the FPGA was idle
I don't think anything I did was particularly novel, as I really just wanted to see how fast I could push a commodity FPGA to it's limit.
Scaling to an ASIC or getting into the billions of params is where the real engineering is! This was just a side project for a side project for me while the FPGA was idle