Spot-on. I came to post this. A CPU core != a Xeon Phi core != a GPU "core". Memory architecture matters a LOT, and much of CPU area is devoted to cache and memory infrastructure. In a GPU, my understanding is every ~32 cores share a small cache and MMU, which makes some SIMD operations / algorithms more challenging to implement. Good for some algorithms, not so great for others.
I think the whole focus on "cores" misses lots of issues. Memory infrastructure is only one. Instruction-level parallelism (superscalar & out-of-order) execution is another - even single-core processors like ye olde Pentium can execute multiple instructions per cycle. It's very easy and tempting to look at the number of cores and use that as a rough estimate of system performance. But this approach will land you WAY off of real-world figures. It's akin to using the number of cylinders in a car's engine to determine how fast it is - sure, to the first order, cylinder count is correlated with engine output and hence car speed, but it's only a very rough correlation.
I think the whole focus on "cores" misses lots of issues. Memory infrastructure is only one. Instruction-level parallelism (superscalar & out-of-order) execution is another - even single-core processors like ye olde Pentium can execute multiple instructions per cycle. It's very easy and tempting to look at the number of cores and use that as a rough estimate of system performance. But this approach will land you WAY off of real-world figures. It's akin to using the number of cylinders in a car's engine to determine how fast it is - sure, to the first order, cylinder count is correlated with engine output and hence car speed, but it's only a very rough correlation.