Comment Comment by Joel_Mckay There are folks trying to make HDL easier, and vendor neutral. Not sure why people were upset by mentioning the project...https://github.com/amaranth-lang/amaranthWhile VHDL makes a fun academic toy language, it has always been Verilog in the commercial settings. Both languages can develop hard to trace bugs when the optimizer decides to simply remove things it thinks are unused. =3 parent Joel_Mckay 7 months ago
https://github.com/amaranth-lang/amaranth
While VHDL makes a fun academic toy language, it has always been Verilog in the commercial settings. Both languages can develop hard to trace bugs when the optimizer decides to simply remove things it thinks are unused. =3