Comment by tasty_freeze

I read the summary but not the paper and it seems like it has nothing to do with physical design. This is a means of making the elaborate/compile/simulation performance of the language faster.

Say someone wrote this code:

    wire [31:0] a, b, c;
    for(i=0; i<32; i=i+1) begin
       assign c[i] = a[i] & b[i];
    end

it sounds like this paper is about recognizing it could be implemented something akin to this:

    wire [31:0] a, b, c;
    assign c = a & b;

Both will produce the exact same gates, but the latter form will compile and simulate faster.