By drawing an analogy between CPU as dynamic interpreter, ASIC manufacturing as AOT compilation, and FPGAs as something between compilation and interpretation(closer to compilation by form),
why aren't ASICs manufactured or FPGAs reconfigured during program execution to speed up hot paths, as a JIT compiler does?
There are two potential problems:
1. The difference between assembly and HDL is much greater than between bytecode and assembly, meaning it is very hard to translate one language into the other efficiently and in a short period of time
2. Hardware manufacturing speed is limited by the speed of physical processes(FPGAs can be reconfigured in tens to hundreds of milliseconds, which is good enough)
There are two potential problems:
1. The difference between assembly and HDL is much greater than between bytecode and assembly, meaning it is very hard to translate one language into the other efficiently and in a short period of time
2. Hardware manufacturing speed is limited by the speed of physical processes(FPGAs can be reconfigured in tens to hundreds of milliseconds, which is good enough)