I've been building high-bandwidth memory streaming interfaces for HBM on VCK5000 & U280 FPGAs in my own language - "SUS".
The goal is to get consistent synthesis to 450MHz such that I can use a narrower 256-bit instead of a 512-bit interface, while maintaining full bandwidth. I've got it working at an FMax ranging 440-490MHz, though there's still some edge cases I need to hammer out.
The goal is to get consistent synthesis to 450MHz such that I can use a narrower 256-bit instead of a 512-bit interface, while maintaining full bandwidth. I've got it working at an FMax ranging 440-490MHz, though there's still some edge cases I need to hammer out.
https://github.com/pc2/sus-xrt