Logic Density (may be inaccurate, also it's not the only metric for performance ): Raipidus 2nm ≈ TSMC N2 > TSMC N3B > TSMC N3E/P > Intel 18A ≈ Samaung 3GAP
But 18A/20A already has PowerVia, while TSMC will implement Backside Power Delivery in A16 (next generation of N2)
Logic Density (may be inaccurate, also it's not the only metric for performance ): Raipidus 2nm ≈ TSMC N2 > TSMC N3B > TSMC N3E/P > Intel 18A ≈ Samaung 3GAP
But 18A/20A already has PowerVia, while TSMC will implement Backside Power Delivery in A16 (next generation of N2)