Comment Comment by eirikbakke In case anyone needs a minimal CPU implementation in 65 lines of Verilog: https://people.csail.mit.edu/ebakke/fic/ https://people.csail.mit.edu/ebakke/fic/code/Fic.v(I wonder if it would convert cleanly to a redstone circuit...) parent eirikbakke 1 year ago
(I wonder if it would convert cleanly to a redstone circuit...)