I know branch prediction is essential if you have instruction pipelining in actual CPU hardware.
It is an interesting thought experiment re instruction pipelining in a virtual machine or interpreter design.
What would you change in a design to allow it ?
Would an asynchronous architecture be necessary ?
How would you merge control flow together efficiently to take advantage of it ?
It is an interesting thought experiment re instruction pipelining in a virtual machine or interpreter design. What would you change in a design to allow it ? Would an asynchronous architecture be necessary ? How would you merge control flow together efficiently to take advantage of it ?