Hardware vendors adhering to C++ memory model to design their chips? I think you got it backwards or I misunderstood your point. Memory barriers exist because of how cache memory hierarchy and coherency protocols are implemented in multi-core chips. And not to "optimize and conform to C++ memory model".
C++ memory model is there to make life of a programmer easier across different micro-architectures because memory model of the micro-architecture is what differs.
C++ memory model is there to make life of a programmer easier across different micro-architectures because memory model of the micro-architecture is what differs.