The comment/question about OUT was more speculation on how it worked on the prototype. But maybe this buffer is part of the architecture, in which case you'd have to consider what happens if it get completely filled (could happen easily with just a few MHz CPU, at standard serial port speeds).
Re. memory: of course with no ternary RAM, you have to somehow encode the trits into bits. But I was more curious about the address bus. So if your memory is organized like this:
--- word #0
--0
--+
-0-
-00 word #1
-0+
-+-
-+0
-++ word #2
how does that map to binary addresses for the RAM chip(s)? What if you
had ternary RAM, would that change how you address it? Does address --0 map to the second lowest/highest (depending on endianness) tryte in word #0, or something entirely different?
Maybe you thought about this a lot more than I have and figured out an ingenious solution. But I would have either gone with word addresses, or power-of-3 units.
And how all of this ties into non-Von Neumann architectures, I still have no clue.
Re. memory: of course with no ternary RAM, you have to somehow encode the trits into bits. But I was more curious about the address bus. So if your memory is organized like this:
how does that map to binary addresses for the RAM chip(s)? What if you had ternary RAM, would that change how you address it? Does address --0 map to the second lowest/highest (depending on endianness) tryte in word #0, or something entirely different?Maybe you thought about this a lot more than I have and figured out an ingenious solution. But I would have either gone with word addresses, or power-of-3 units.
And how all of this ties into non-Von Neumann architectures, I still have no clue.