I would've expected some information on the architecture, maybe even a simulator. That should surely already have existed before any working hardware?
Let's try to make sense of that code shown:
...
jsr println
anyi r3 r0 #1324
jsr println
anyi r3 r0 #1412
jsr println
hlt
r0 appears to be the zero register, "anyi" combines that with an immediate to load a pointer to the string to print into r3. The immediate field is 12 trits, so we have a maximum address range of 531441 (trytes?)
The encoding for the "jsr println" is always the same, so it's using absolute addresses, range is 3^20 or slightly less than 3.5G. Or would be if we were allowing negative addresses, since it appears to be balanced ternary (+--+00 = 144 decimal)
Next bit of code is println, the address matches the one from jsr.
println:
ld r2 0(r3) ;get char
jeq r2 r0 exit_println ;exit if nul
out 50(r0) r2 ;output to console0?
out 60(r0) r2 ;output to console1?
addi r3 r3 #4 ;next char - why add 4?
jmp println ;loop
exit_println:
anyi r4 r0 #10 ;ASCII LF
out 60(r0) r4 ;output to console1?
anyi r4 r0 #13 ;ASCII CR
out 60(r0) r4 ;output to console1?
jr r26 ;return (r26 = link register set by jsr)
I'm not sure if this is supposed to be a word-addressed machine. Or would be better if it actually was. The addressing unit appears to be 6-trit "trytes", but loads only work when aligned to 4? Which seems a bit (no pun intended) inconvenient for a ternary computer! Is there no "load tryte" instruction?
Jump instructions are encoded relative to the next instruction, with a 12-trit immediate. Seems fine, but a bit inconsistent with how jsr uses absolute addresses. Also again every instruction is 4 trytes, so we could drop the low bits and shift... ah, I'm forgetting that it's ternary, never mind.
Separate I/O space, seems a bit un-RISCy. I personally happen to like x86, but even there it's considered a legacy feature nowadays.
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This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product.
Let's try to make sense of that code shown:
r0 appears to be the zero register, "anyi" combines that with an immediate to load a pointer to the string to print into r3. The immediate field is 12 trits, so we have a maximum address range of 531441 (trytes?)The encoding for the "jsr println" is always the same, so it's using absolute addresses, range is 3^20 or slightly less than 3.5G. Or would be if we were allowing negative addresses, since it appears to be balanced ternary (+--+00 = 144 decimal)
Next bit of code is println, the address matches the one from jsr.
I'm not sure if this is supposed to be a word-addressed machine. Or would be better if it actually was. The addressing unit appears to be 6-trit "trytes", but loads only work when aligned to 4? Which seems a bit (no pun intended) inconvenient for a ternary computer! Is there no "load tryte" instruction?Jump instructions are encoded relative to the next instruction, with a 12-trit immediate. Seems fine, but a bit inconsistent with how jsr uses absolute addresses. Also again every instruction is 4 trytes, so we could drop the low bits and shift... ah, I'm forgetting that it's ternary, never mind.
Separate I/O space, seems a bit un-RISCy. I personally happen to like x86, but even there it's considered a legacy feature nowadays.
---
This may sound harsh, but to me the architecture looks both fairly conventional, and at the same time like a bit of a mess, which would be fine for a hobby project, but not for something with a website making grandiose claims and clearly intending to be a commercial product.